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TS3V330RGYR

TS3V330RGYR资料
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File Size : 116 KB Manufacturer:TI Description:With chip select (CS) inactive (high), the ADDRESS and I/O CLOCK inputs are initially disabled and DATA OUT is in the high-impedance state. When the serial interface takes CS active (low), the conversion sequence begins with the enabling of I/O CLOCK and ADDRESS and the removal of DATA OUT from the high-impedance state. The host then provides the 4-bit channel address to ADDRESS and the I/O CLOCK sequence to I/O CLOCK. During this transfer, the host serial interface also receives the previous conversion result from DATA OUT. I/O CLOCK receives an input sequence that is between 10 and 16 clocks long from the host. The first four I/O clocks load the address register with the 4-bit address on ADDRESS selecting the desired analog channel and the next six clocks providing the control timing for sampling the analog input.

	1PCS	100PCS	1K	10K
价格


型号：TS3V330RGYR 厂家：TI 封装：QFN 批号：07+G4 数量：48 说明：QQ：104735486 611606076


运费：运费到付10.00元（快递）20.00元（顺风）所在地：深圳新旧程度：