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SN74LVCC3245APW

SN74LVCC3245APW资料
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File Size : 116 KB Manufacturer:TI Description:SIGNAL DESCRIPTIONS See Figure 1, Logic Diagram, and Table 1, Signal Names, for a brief overview of the signals connect- ed to this device. Address Inputs (A0-A17). The Address Inputs select the cells in the memory array to access dur- ing Bus Read operations. During Bus Write opera- tions they control the commands sent to the Command Interface of the internal state machine. Data Inputs/Outputs (DQ0-DQ7). The Data In- puts/Outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine. Chip Enable (E). The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write op- erations to be performed. When Chip Enable is High, V IH, all other pins are ignored. Output Enable (G). The Output Enable, G, con- trols the Bus Read operation of the memory. Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memorys Com- mand Interface. Reset/Block Temporary Unprotect (RP). The Re- set/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to tem- porarily unprotect all blocks that have been pro- tected. On the M29F002BNT the pin is not connected internally and this feature is not avail- able.

	1PCS	100PCS	1K	10K
价格


型号：SN74LVCC3245APW 厂家：TI 封装：TSSOP24 批号：07+G4 数量：92 说明：QQ：104735486 611606076


运费：运费到付10.00元（快递）20.00元（顺风）所在地：深圳新旧程度：