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PNX0102AET

PNX0102AET资料
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File Size : 116 KB Manufacturer:PHI Description:Intrinsic deterministic device jitter is a measurement of the deterministic jitter contribution from the device. It is derived by the equation (DJ(OUT)C DJ(IN) ), where DJ(OUT) is the total peak-to-peak deterministic jitter measured at the output of the device in pspp. DJ(IN) is the peak-to-peak deterministic jitter of the pattern generator driving the device. The SN65LVCP40 built-in passive input equalizer compensates for ISI. For a 20-inch FR4 transmission line with 8-mil trace width, the LVCP40 typically reduces jitter by 60 ps from the device input to the device output. Absolute deterministic output jitter reflects the deterministic jitter measured at the SN65LVCP40 output. The value is a real measured value with a Bit error tester as described in Figure 7. The absolute DJ reflects the sum of all deterministic jitter components accumulated over the link: DJ(absolute) = DJ(Signal generator) + DJ(transmission line) + DJ(intrinsic(LVCP40)).

	1PCS	100PCS	1K	10K
价格


型号：PNX0102AET 厂家：PHI 封装：BGA 批号：04+/05+ 数量：16 说明：现货库存,特价热卖


运费：运费到付10.00元（快递）20.00元（顺风）所在地：深圳新旧程度：