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LTC1625CGN

LTC1625CGN资料
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File Size : 116 KB Manufacturer:LINEAR Description:NOTES 1Typicals represent average readings at 25C, VDD = 5 V. 2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi- tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Test Circuits. 3INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V. DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions. See Figure 10. 4Resistor terminals A, B, W have no limitations on polarity with respect to each other. 5Guaranteed by design and not subject to production test. 6PDISS is calculated from (I DD VDD). CMOS logic level inputs result in minimum power dissipation. 7Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest band- width. The highest R value results in the minimum overall power consumption. 8All dynamic characteristics use V DD = 5 V. 9See timing diagram for location of measured values. Specifications subject to change without notice.

	1PCS	100PCS	1K	10K
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型号：LTC1625CGN 厂家：LINEAR 封装：SSOP16 批号：04+ 数量：5422 说明：QQ：104735486 611606076


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