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LMV344IPWRQ1

LMV344IPWRQ1资料
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File Size : 116 KB Manufacturer:TI Description:Writing to the SRAM is accomplished when the chip select (CS) and write enable (WE) inputs are both LOW. Data on the eight input/output pins (I/O0 through I/O7) of the device is then written into the memory location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking chip select (CE) and output enable (OE) LOW while write enable (WE) remains inactive or HIGH. Under these con- ditions, the contents of the memory location specified on the address pins (A0 through A18) will appear on the eight appro- priate data input/output pins (I/O0 through I/O7).The eight in- put/output pins (I/O0 through I/O7) are placed in a high imped- ance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW).

	1PCS	100PCS	1K	10K
价格


型号：LMV344IPWRQ1 厂家：TI 封装：TSSOP16 批号：07+G4 数量：16 说明：QQ：104735486 611606076


运费：运费到付10.00元（快递）20.00元（顺风）所在地：深圳新旧程度：