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FM25CL64-DG

FM25CL64-DG资料
	FM25CL64-DG PDF Download

File Size : 116 KB Manufacturer:RAMTRON Description:BURST CONFIGURATION COMMAND: The Program Burst Configuration Register command is used to program the burst configuration register. The burst configuration register determines several parameters that control the read operation of the device. Bit B15 determines whether synchronous burst reads are enabled or asynchronous reads are enabled. Since the page read operation is an asynchronous operation, bit B15 must be set for asynchronous reads to enable the page read feature. Bit B14 determines whether a four-word page or an eight-word page will be used. The rest of the bits in the burst configuration register are used only for the burst read mode. Bits B13 - B11 of the burst configuration register determine the clock latency for the burst mode. The latency can be set to two, three, four, five or six cycles. The clock latency versus input clock frequency table is shown on page 20. The Burst Read Waveform as shown on page 31 illustrates a clock latency of four; the data is output from the device four clock cycles after the first valid clock edge following the high-to-low AVD edge. The B10 bit of the configuration register determines the polarity of the WAIT signal. The B9 bit of the burst configuration register determines the number of clocks that data will be held valid (see Figure 4). The Hold Data for 2 Clock Cycles Read Waveform is shown on page 31. The clock latency is not affected by the value of the B9 bit. The B8 bit of the burst configuration register deter- mines when the WAIT signal will be asserted. When synchronous burst reads are enabled, a linear burst sequence is selected by setting bit B7. Bit B6 selects whether the burst starts and the data output will be relative to the falling edge or the rising edge of the clock. Bits B2 - B0 of the burst configuration register determine whether a continuous or fixed-length burst will be used and also determine whether a four-, eight- or sixteen-word length will be used in the fixed-length mode. When a four-, eight- or sixteen-word burst length is selected, Bit B3 can be used to select whether burst accesses wrap within the burst length boundary or whether they cross word length boundaries to perform linear accesses (see Table 5). All other bits in the burst configuration register should be programmed as shown on page 20. The default state (after power-up or reset) of the burst configuration register is also shown on page 20.


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1PCS

100PCS

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价格

型号：FM25CL64-DG
厂家：RAMTRON
封装：QFN
批号：08+
数量：785
说明：

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容量:	64Kb
最大工作电流:	7mA
最大读写频率:	16MHz
封装:	SOIC8
电压:	3.0-3.6V
AEC-Q100认证:	Grade 1

现有文件

数据手册:

FM25CL64-GAds

64Kbit位非易失性铁电存储器
• 结构容量为8，92 x 8位
• 读/写次数无限制
• 写数据无延迟
• 采用先进的高可靠性铁电制造工艺

高速串行外设接口- SPI
• 总线频率可达16MHz
• 硬件上可直接替换EEPROM
• SPI模式0&3（CPOL,CPHA=0,0&1,1）