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ED8903A

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File Size : 116 KB Manufacturer:SAMSUNG Description:All digital clocks generate unwanted energy in their harmonics. Conventional digital clocks are square waves with a duty cycle that is very close to 50%. Because of this 50/50 duty cycle, digital clocks generate most of their harmonic energy in the odd harmonics, i.e., third, fifth, seventh, etc. It is possible to reduce the amount of energy contained in the fundamental and odd harmonics by increasing the bandwidth of the funda- mental clock frequency. Conventional digital clocks have a very high Q factor, which means that all of the energy at that frequency is concentrated in a very narrow bandwidth, conse- quently, higher energy peaks. Regulatory agencies test electronic equipment by the amount of peak energy radiated from the equipment. By reducing the peak energy at the funda- mental and harmonic frequencies, the equipment under test is able to satisfy agency requirements for EMI. Conventional methods of reducing EMI have been to use shielding, filtering, multilayer PCBs, etc. The SM561 uses the approach of reducing the peak energy in the clock by increasing the clock bandwidth, and lowering the Q.

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型号：ED8903A 厂家：SAMSUNG 封装：PLCC 批号：04+ 数量：890 说明：QQ：104735486 611606076


运费：运费到付10.00元（快递）20.00元（顺风）所在地：深圳新旧程度：