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CDCE913PW

CDCE913PW资料
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File Size : 116 KB Manufacturer:TI Description:PCM INTERFACE The FSX and FSR frame sync inputs determine the begin- ning of the 8-bit transmit and receive time-slots respectively. They may have any duration from a single cycle of BCLK HIGH to one MCLK period LOW. Two different relationships may be established between the frame sync inputs and the actual time-slots on the PCM busses by setting bit 3 in the Control Register (see Table 2). Non-delayed data mode is similar to long-frame timing on the TP3050/60 series of de- vices (COMBO); time-slots begin nominally coincident with the rising edge of the appropriate FS input. The alternative is to use Delayed Data mode, which is similar to short-frame sync timing on COMBO, in which each FS input must be high at least a half-cycle of BCLK earlier than the time-slot. The Time-Slot Assignment circuit on the device can only be used with Delayed Data timing.

	1PCS	100PCS	1K	10K
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型号：CDCE913PW 厂家：TI 封装：TSSOP14 批号：07+G4 数量：20 说明：QQ：104735486 611606076


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