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CD74ACT164M

CD74ACT164M资料
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File Size : 116 KB Manufacturer:TI Description:DQP[A:D]. In addition, the address for the subsequent access (Read/Write/Deselect) is latched into the Address Register (provided the appropriate control signals are asserted). On the next clock rise the data presented to DQs and DQP[A:D] (or a subset for Byte Write operations, see Write Cycle Description table for details) inputs is latched into the device and the write is complete. The data written during the Write operation is controlled by BW[A:D] signals. The CY7C1350G provides byte write capability that is described in the Write Cycle Description table. Asserting the Write Enable input (WE) with the selected Byte Write Select (BW[A:D]) input will selectively write to only the desired bytes. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Byte write capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple byte write operations. Because the CY7C1350G is a common I/O device, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQs and DQP[A:D] inputs. Doing so will tri-state the output drivers. As a safety precaution, DQs and DQP[A:D] are automatically tri-stated during the data portion of a write cycle, regardless of the state of OE.


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	1PCS	100PCS	1K	10K
价格


型号：CD74ACT164M 厂家：TI 封装：SOP14 批号：07+G4 数量：260 说明：QQ：104735486 611606076


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